/**
 @file sys_usw_phy.h

 @date 2021-11-19

 @version v2.0

 The file contains all phy related APIs of sys layer
*/

#ifndef _SYS_USW_PHY_H
#define _SYS_USW_PHY_H
#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_const.h"
#include "ctc_chip.h"
#include "ctc_debug.h"
#include "sys_usw_common.h"

/****************************************************************
*
* Defines and Macros
*
****************************************************************/

#define SYS_PHY_DBG_OUT(level, FMT, ...) \
    do { \
        CTC_DEBUG_OUT(port, phy, PHY_SYS, level, FMT, ##__VA_ARGS__); \
    } while (0)


extern int32
sys_usw_phy_set_phy_mapping(uint8 lchip, ctc_chip_phy_mapping_para_t* phy_mapping_para);

extern int32
sys_usw_phy_get_phy_mapping(uint8 lchip, ctc_chip_phy_mapping_para_t* p_phy_mapping_para);

extern void
sys_usw_phy_link_event_polling_cb(uint8 lchip, uint32 gport);

extern int32
sys_usw_phy_set_phy_register(uint8 lchip, ctc_chip_phy_shim_t* p_register);

extern int32
sys_usw_phy_set_phy_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, void* p_value);

extern int32
sys_usw_phy_get_phy_property(uint8 lchip, uint16 lport, ctc_port_property_t port_prop, void* p_value);

extern int32
sys_usw_phy_get_phy_register_exist(uint8 lchip, uint16 lport);

extern int32
sys_usw_phy_init(uint8 lchip, ctc_port_global_cfg_t* p_port_global_cfg);

extern int32
sys_usw_phy_deinit(uint8 lchip);
#ifdef __cplusplus
}

#endif

#endif

